Electronic apparatus, control circuit for electronic apparatus, and method of controlling electronic apparatus

ABSTRACT

The present invention relates to an electronic apparatus, a control circuit of an electronic apparatus, and a method of controlling an electronic apparatus that change different states by a predetermined input operation, and has an object of providing an electronic apparatus, a control circuit of an electronic apparatus, and a method of controlling an electronic apparatus that prevent the transition of states due to an unintentional operation. A SUSPEND/RESUME signal generation part  151  for generating a SUSPEND/RESUME signal whose level becomes LOW when a SUSPEND/RESUME button  110  is pressed and a SUSPEND/RESUME signal control part  152  for maintaining the LOW-level period of the SUSPEND/RESUME signal generated by the SUSPEND/RESUME signal generation part  151  within a predetermined period T 0  are provided between the SUSPEND/RESUME button  110  and a chip set  139  that achieves a SUSPEND or RESUME function when the SUSPEND/RESUME button  110  is pressed.

TECHNICAL FIELD

[0001] The present invention relates to electronic apparatuses,-controlcircuits for electronic apparatuses, and methods of controllingelectronic apparatuses, and more particularly to an electronicapparatus, a control circuit for an electronic apparatus, and a methodof controlling an electronic apparatus that change different states by apredetermined input operation.

[0002] Recently, a SUSPEND/RESUME function has been applied to anelectronic apparatus such as a personal computer as a part of powermanagement.

[0003] The SUSPEND/RESUME function is a sort of power-saving function ofa personal computer. According to the SUSPEND/RESUME function, thesystem of a personal computer is caused to stop an operation of a harddisk or a CPU by operating a SUSPEND/RESUME button so as to change thestate of the personal computer to a low power consumption state, and iscaused to resume the operation of the hard disk or the CPU by operatingthe SUSPEND/RESUME button again.

[0004] A standard called ACPI (Advanced Configuration and PowerManagement Interface) is established for the power management of apower-saving function such as this SUSPEND/RESUME function of a personalcomputer. The power management of a personal computer is usually basedon the ACPI standard.

[0005] Under the ACPI standard, it is required to have a functionenabling a shut-off of power other than the SUSPEND/RESUME function.

BACKGROUND ART

[0006] Some chip sets house power management functions conforming to theACPI standard so that the power management function conforming to theACPI standard can be easily mounted.

[0007]FIG. 1 is a block diagram of a conventional electronic apparatus.

[0008] A conventional electronic apparatus 1 includes a chip set 2connected to a SUSPEND/RESUME button 3. The chip set 2 causes aninterrupt for a SUSPEND or RESUME operation to a processing part 4 basedon an operation of the SUSPEND/RESUME button 3. After performing anoperation such as a save of data in process in accordance with theinterrupt for a SUSPEND or RESUME operation caused by the chip set 2,the processing part 4 controls a power control part 5 connected to thechip set 2 via the chip set 2 to stop a hard disk or a CPU so that poweris supplied to a minimum essential part such as a part for dataretention.

[0009] The SUSPEND/RESUME button 3 has its one end grounded and theother end connected to the chip set 2. A constant voltage Vc is appliedvia a resistor R between the SUSPEND/RESUME button 3 and the chip set 2.

[0010] If the SUSPEND/RESUME button 3 is switched OFF, the constantvoltage Vc is applied to the chip set 2 via the resistor R. Therefore, aSUSPEND/RESUME control terminal Tc of the chip set 2, to which terminalthe SUSPEND/RESUME button 3 is connected, is set to a HIGH level.

[0011] If the SUSPEND/RESUME button 3 is switched ON, the constantvoltage Vc is applied to a ground through the resistor R and theSUSPEND/RESUME button 3. Therefore, the SUSPEND/RESUME control terminalTc of the chip set 2, to which terminal the SUSPEND/RESUME button 3 isconnected, is set to a LOW level.

[0012] The chip set 2 monitors a change in the level of theSUSPEND/RESUME terminal Tc. If the level of the SUSPEND/RESUME terminalTc changes from the HIGH level to the LOW level while the processingpart 4 is in a normal operating state, the chip set 2 causes aninterrupt for a SUSPEND operation to the processing part 4. When thechip set 2 causes the interrupt for the SUSPEND operation to theprocessing part 4, the processing part 4 controls operations to be setin a SUSPEND state after saving the data in process.

[0013] If the level of the SUSPEND/RESUME terminal Tc changes again fromthe HIGH level to the LOW level while the processing part 4 is in theSUSPEND state, the chip set 2 causes an interrupt for a RESUME operationto the processing part 4. When the chip set 2 causes the interrupt forthe RESUME operation to the processing part 4, the processing part 4returns the saved data to return to the normal operating state.

[0014] Further, the chip set 2 is provided with a function enabling ashut-off of power by the operation of the SUSPEND/RESUME button 3. Thechip set 2 monitors the level change of the SUSPEND/RESUME controlterminal Tc. If the level of the SUSPEND/RESUME control terminal Tc ismaintained at the LOW level, that is, the SUSPEND/RESUME button 3 ismaintained in a pressed state, for a predetermined period of time, forinstance, four seconds, the chip set 2 directly controls the powercontrol part 5 to shut off the power irrespective of the states of theprocessing part 4.

[0015]FIG. 2 is a waveform chart of an operation of the conventionalelectronic apparatus. FIG. 2(A) shows a signal supplied to theSUSPEND/RESUME control terminal Tc of the chip set 2 by the operation ofthe SUSPEND/RESUME button 3, FIG. 2(B) shows the SUSPEND state, and FIG.2(C) shows a POWER SHUT-OFF state.

[0016] If the SUSPEND/RESUME button 3 is operated at a time t0, theSUSPEND/RESUME control terminal Tc of the chip set 2 changes from thehigh level to the low level as shown in FIG. 2(A).

[0017] When detecting the level change of the SUSPEND/RESUME controlterminal Tc from the HIGH level to the LOW level, the chip set 2 causesan interrupt for the SUSPEND operation to the processing part 4. Wheninterrupted by the chip set 2, the processing part 4 returnably savesdata in process, and then controls the power control part 5 via the chipset 2 so as to shut off the power supply to a predetermined part. Thus,the processing part 4 is set in the SUSPEND state as shown in FIG. 2(B).

[0018] Further, the chip set 2 houses a timer. When the level change ofthe SUSPEND/RESUME control terminal Tc from the HIGH level to the LOWlevel is detected, the timer housed in the chip set 2 is activated tocount time while the SUSPEND/RESUME button 3 is in the pressed state,that is, while the SUSPEND/RESUME control terminal Tc of the chip set 2is maintained at the LOW level as indicated by a solid line in FIG.2(A). When the timer counts time until a time t1 at which apredetermined period T0, for instance, four seconds, passes, the chipset 2 controls the power control part 5 to command a so-called POWERSHUT-OFF operation that shuts off all the power.

[0019] If pressing the SUSPEND/RESUME button 3 ends at a time t2 atwhich the predetermined period T0, for instance, four seconds, does notpass while the timer counts time, the chip set 2 maintains the system ofthe processing part 4 in the SUSPEND state.

[0020] Next, if the SUSPEND/RESUME button 3 is pressed at a time t3 sothat the level of the SUSPEND/RESUME control terminal Tc of the chip set2 changes again from the HIGH level to the LOW level as indicated by abroken line in FIG. 2(A), the chip set 2 causes an interrupt for theRESUME operation to the processing part 4. The processing part 4, basedon the interrupt for the RESUME operation, controls the power controlpart 5 via the chip set 2 to turn on the power, and by returning thedata saved at the time of the SUSPEND state, enables a processingoperation to be resumed from a state before the SUSPEND state.

[0021] As described above, the chip set 2 houses a function performingthe SUSPEND or RESUME operation, or the POWER SHUT-OFF operationdepending on a pressing time of the SUSPEND/RESUME button 3.

[0022] However, in the POWER SHUT-OFF operation employing theconventional SUSPEND/RESUME button 3, the power is shut off by pressingthe SUSPEND/RESUME button 3 for the predetermined period (four seconds).On the other hand, in the SUSPEND or RESUME operation by pressing theSUSPEND/RESUME button 3, it takes time in saving or returning data sothat the SUSPEND or RESUME state is prevented from being set immediatelyafter the operation of the SUSPEND/RESUME button 3. Therefore, instarting the SUSPEND or RESUME operation, the SUSPEND/RESUME button 3 isprone to be pressed for a longer period than necessary.

[0023] Therefore, if a user keeps pressing the SUSPEND/RESUME button 3for a longer period than necessary in starting the SUSPEND or RESUMEoperation since it takes time in activating the SUSPEND/RESUME function,the power is shut off to erase the data in process, thus causing aproblem.

[0024] The present invention is made in the light of the above-describedpoint, and has an object of providing an electronic apparatus, a controlcircuit for an electronic apparatus, and a method of controlling anelectronic apparatus which can prevent the transition of states due toan unintentional operation.

DISCLOSURE OF THE INVENTION

[0025] The present invention, which is an electronic apparatus changingstates thereof based on a predetermined input operation, ischaracterized by including: input means for performing the predeterminedinput operation; input operation detection means for detecting apresence or absence of the predetermined input operation to the inputmeans; state transition control means for changing a state of theapparatus from a first state to a second state when the input operationdetection means detects an operation of the input means, and changingthe state of the apparatus to a third state when a continuation of theoperation of the input means for a predetermined period or longer isdetected, the first, second, and third states being different from oneanother; and nullification means for nullifying the operation of theinput means before a passage of the predetermined period.

[0026] Further, the present invention is characterized in that the inputoperation detection means includes detection signal generation means forgenerating a detection signal of a certain state based on the operationof the input means, and that the nullification means includes detectionsignal restriction means for restricting a period of the certain stateof the detection signal within the predetermined period.

[0027] According to the present invention, by restricting the period ofthe predetermined input operation by the input means within thepredetermined period, the state of the apparatus is prevented from beingchanged from the first state to the second state even if the input meansis operated for the predetermined period or longer. Therefore, anunnecessary state transition can be prevented, thus increasing theoperability of the electronic apparatus.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028]FIG. 1 is a block diagram of a conventional electronic apparatus;

[0029]FIG. 2 is a waveform chart of an operation of the conventionalelectronic apparatus;

[0030]FIG. 3 is a perspective view of a display surface of an embodimentof the present invention;

[0031]FIG. 4 is a perspective view of a reverse side of the embodimentof the present invention;

[0032]FIG. 5 is a side view of the embodiment of the present invention;

[0033]FIG. 6 is a block diagram of the embodiment of the presentinvention;

[0034]FIG. 7 is a block diagram of a SUSPEND/RESUME signal generationcircuit of the embodiment of the present invention;

[0035]FIG. 8 is a circuit diagram of a SUSPEND/RESUME signal controlpart of the embodiment of the present invention; and

[0036]FIG. 9 is a waveform chart of an operation of the SUSPEND/RESUMEsignal control part of the embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0037]FIG. 3 is a perspective view of a display surface of an embodimentof the present invention, FIG. 4 is a perspective view of a reverse sideof the embodiment of the present invention, and FIG. 5 is a side view ofthe embodiment of the present invention.

[0038] An electronic apparatus 100 of this embodiment is a portablecomputer apparatus of a pen-input type. As shown in FIG. 3, a displayscreen 101, a status display 102, a penholder 103, a microphone 104, aspeaker 105, and a grip part 106 are provided on the front surface ofthe apparatus.

[0039] The display screen 101 includes a touch panel so that data can berecognized thereon and inputted thereto.

[0040] The status display 102 is provided on the upper left side of thedisplay screen 101 to display states of the apparatus. The statusdisplay 102 displays a variety of states such as a state of access to anHDD, a state of battery charge, and a SUSPEND state.

[0041] The penholder 103 is formed on the upper right side of thedisplay screen 101 to hold a pen for indication for a data input. Thepen is extracted from the penholder 103 when the apparatus is operated.Indications are given and operations are performed with respect to theapparatus by pressing the display screen 101 by means of the penextracted from the penholder 103.

[0042] The microphone 104 is provided on the upper right side of thedisplay screen 101. The microphone 104 is used for inputting voice asdata.

[0043] The speaker 105 is provided on the lower right side of thedisplay screen 101. The speaker 105 is used for an audio output. Theleft side of the display screen 101 is designed to be the grip part 106for the user holding the apparatus in a portable use thereof.

[0044] A PC card slot 107, a modem port 108, an IrDA port 109, and aSUSPEND/RESUME button 110 are provided on the upper surface of theapparatus.

[0045] The PC card slot 107 conforms, for instance, to PCMCIA, and an ICcard conforming to PCMCIA is inserted thereinto from outside. Thefunctions of the apparatus can be expanded by inserting the PC card.

[0046] A telephone line is connected to the modem port 108. Datacommunication is enabled by connecting the telephone line to the modemport 108.

[0047] The IrDA port 109 enables infrared communication conforming toIrDA (Infrared Data Association). The SUSPEND/RESUME button 110 is apress button for commanding a SUSPEND or RESUME operation. If theSUSPEND/RESUME button 110 is pressed while the apparatus is in a normaloperating state, the apparatus is set in the SUSPEND state that is apower-saving mode. If the SUSPEND/RESUME button 110 is pressed while theapparatus is in the SUSPEND state or in a POWER SHUT-OFF state, theapparatus returns to the normal operating state.

[0048] Further, a USB port 111 and a battery pack attachment part 112are provided on the left side face of the apparatus.

[0049] The USB port 111 is a port conforming to the USB (UniversalSerial Bus) standard. A variety of peripheral devices conforming to theUSB standard, such as a modem, a TA, a printer, a keyboard, and a mouse,are connected to the USB port 111.

[0050] A battery pack for driving the apparatus is attached to thebattery pack attachment part 112.

[0051] As shown in FIG. 4, a variety of attachment coupling parts 114are formed on the reverse side of the apparatus. An option such as ahand strap is coupled to a corresponding one of the attachment couplingparts 114.

[0052] A heat sink vent 115, a system interface port 116, and a dockingcontact 117 are provided on the lower surface of the apparatus. The heatsink vent 115 is a vent for emitting outside heat generated in theapparatus. The heat sink vent 115 emits the heat generated in drivingthe apparatus so that an optimum temperature is maintained therein.

[0053] The system interface port 116 is a connection port exclusivelyfor the system, and a peripheral device conforming to the port isconnected thereto.

[0054] The docking contact 117 is a contact for a connection with anexpansion station and connects the apparatus and the expansion station.

[0055] Further, a DC-input connector 118, an I/O connector part 119, aheadphone jack 120, a microphone jack 121, and a PS/2 port 122 areprovided on the right side face of the apparatus.

[0056] An AC adapter is connected to the DC-input connector 118 so thata DC voltage is applied. The I/O connector part 119 has a variety of I/Oconnectors provided therein. A headphone is connected to the headphonejack 120, and a microphone is connected to the microphone jack 121. Akeyboard or a mouse conforming to PS/2 is connected to the PS/2 port122.

[0057] As shown in FIG. 5, a video port 123, a serial port 124, aparallel port 125, and a reset button 126 are provided in the I/Oconnector part 119 of the apparatus.

[0058] A display is connected to the video port 123. A connectorconforming to RS232C is connected to the serial port 124 for a datainput and output. The parallel port 125 is a so-called printer port, towhich a parallel connector such as a printer is connected.

[0059] The reset button 126 is operated when the apparatus is activatedafter power is turned OFF. That is, the reset button 126 is operated toperform a so-called reset operation. Once the reset operation isperformed, data in process is erased. Therefore, the reset button 126 isdesigned to be pressed by a pen point so as not to be operated easily.The reset button 126 is operated at a time of an abnormal operation.

[0060]FIG. 6 is a block diagram of the embodiment of the presentinvention.

[0061] The electronic apparatus 100 includes a CPU 131, a bridge circuit132, a RAM 133, a graphics LSI 134, a PC card controller 135, a modem136, an IrDA controller 137, a PCI bus 138, a chip set 139, an HDD 140,a ROM 141, a touch panel controller 142, a sound controller 143, a powercontroller 144, a SUSPEND/RESUME signal generation circuit 145, and anISA bus 146.

[0062] The CPU 131 performs operations in accordance with programsstored in the HDD 140.

[0063] The bridge circuit 132 is connected to the CPU 131, the RAM 133,and the PCI bus 136. The RAM 133 is employed as working storage foroperations performed by the CPU 131.

[0064] The graphics LSI 134 is connected between a display 101 a and thePCI bus 138 to process data to be displayed and display the data on thedisplay 101 a of the display screen 101.

[0065] The PC card controller 135 is connected between the PC card slot107 and the PCI bus 138 to connect the PC card attached to the PC cardslot 107 to the PCI bus 138. The modem 136 is connected between themodem port 109 and the PCI bus 138 to provide an interface between thePCI bus 138 and the telephone line.

[0066] The USB port 111, the reset button 126, the PCI bus 138, the HDD140, the ROM 141, the power controller 144, the SUSPEND/RESUME signalgeneration circuit 145, and an ISA bus 146 are connected to the chip set139, which provides an interface with the peripheral devices and, aswill be described later, performs a variety of functions including aSUSPEND/RESUME function.

[0067] The HDD 140 stores the programs to be executed in the apparatusand data. The programs stored in the HDD 140 are read out to the RAM 133and executed by the CPU 131 upon request.

[0068] Drive power is supplied from the battery pack 133 or the DC-inputport 118 to the power controller 144. The power controller 144 generatesdriving power for driving parts such as the CPU 131 and the HDD 140 fromthe drive power supplied from the battery pack 133 or the DC input port118, and supplies the driving power to the parts. The power controller144 is connected to the chip set 139, and controls the SUSPEND andRESUME operations, and a POWER SHUT-OFF operation based on a controlsignal supplied from the chip set 139.

[0069] The SUSPEND/RESUME signal generation circuit 145 is connectedbetween the SUSPEND/RESUME button 110 and the chip set 139 to generate aSUSPEND/RESUME signal based on an operation of the SUSPEND/RESUME button110. As will be described later, the SUSPEND/RESUME signal generationcircuit 145 generates the SUSPEND/RESUME signal so as to set a LOW-levelperiod thereof shorter than a predetermined period of time.

[0070] Further, the reset button 126 is connected to the chip set 139.If the reset button 126 is operated, the chip set 139 supplies a commandfor the POWER SHUT-OFF operation to the power controller 144, and afterthe power is shut off, the chip set 139 controls the power controller144 to turn on the power again to activate the apparatus.

[0071] The IrDA controller 137, the ROM 141, the touch panel controller142, and the sound controller 143 are connected to the ISA bus 146.

[0072] The IrDA controller 137 is connected between the IrDA port 108and the ISA bus 146 so as to provide an interface between a signaltransmitted or received by means of infrared by the IrDA port 108, andthe PCI bus 138.

[0073] The ROM 141 stores a boot program. The boot program stored in theROM 141 is executed by the CPU 131 at a time of the reset operation orat a time of turning on the power so as to set the apparatus in anenabled state.

[0074] The touch panel controller 142 is connected between a touch panel101 b forming the display screen 101 together with the display 101 a,and the ISA bus 146 so as to provide an interface therebetween.

[0075] The sound controller 143 is connected between the ISA bus, andthe headphone and microphone Jacks 120 and 121 to perform speechprocessing.

[0076] The USB port 111 is connected to the chip set 139 so thatcommunication is made with the peripheral devices connected to the USBport 111.

[0077] Next, a detailed description will be given of the SUSPEND/RESUMEsignal generation circuit 145.

[0078]FIG. 7 is a block diagram of the SUSPEND/RESUME signal generationcircuit of the embodiment of the present invention.

[0079] The SUSPEND/RESUME signal generation circuit 145 of thisembodiment includes a SUSPEND/RESUME signal generation part 151 and aSUSPEND/RESUME signal control part 152.

[0080] The SUSPEND/RESUME signal generation part 151 includes a constantvoltage source 153 and a resistor 154. A constant voltage supplied fromthe constant voltage source 153 is reduced through the resistor 154 tobe applied to one end T10 of the SUSPEND/RESUME button 110. TheSUSPEND/RESUME button 110 has its one end T10 connected to theSUSPEND/RESUME signal generation part 151 and is connected to aSUSPEND/RESUME control terminal TO of the chip set 139 via theSUSPEND/RESUME signal control part 152. The other end T11 of theSUSPEND/RESUME button 110 is grounded. The SUSPEND/RESUME button 110 hasits both ends T10 and T11 opened in a normal state, and short-circuitedin a pressed state.

[0081] Therefore, in the normal state in which the SUSPEND/RESUME button110 is not operated, the constant voltage supplied from theSUSPEND/RESUME signal generation part 151 is applied to theSUSPEND/RESUME signal control part 152. That is, the input of theSUSPEND/RESUME signal control part 152 is set to a HIGH level. On theother hand, if the SUSPEND/RESUME button 110 is pressed, both ends T10and T11 of the SUSPEND/RESUME button 110 are short-circuited, so thatthe constant voltage generated in the SUSPEND/RESUME signal generationpart 151 is applied to a ground. That is, the input of theSUSPEND/RESUME signal control part is set to a LOW level.

[0082] The SUSPEND/RESUME signal control part 152 restricts theLOW-level state period of the input to less than a predetermined periodof time.

[0083]FIG. 8 is a circuit diagram of the SUSPEND/RESUME signal controlpart of the embodiment of the present invention.

[0084] The SUSPEND/RESUME signal control part 152 includes a capacitor155, a resistor 156, a diode 157, and an amplifier circuit 158.

[0085] The capacitor 155 has a first end connected to the connectionpoint of the SUSPEND/RESUME button 110 and the SUSPEND/RESUME signalgeneration part 151. The capacitor 155 generates a differentiatedwaveform of the signal at the connection point of the SUSPEND/RESUMEbutton 110 and the SUSPEND/RESUME signal generation part 151.

[0086] The capacitor 155 has a second end connected to the amplifiercircuit 158. The amplifier circuit 158 is supplied with thedifferentiated waveform of the SUSPEND/RESUME signal, and outputs asignal whose level becomes LOW when the level of the differentiatedwaveform is below a predetermined level, and becomes HIGH when the levelof the differentiated waveform is above the predetermined level.

[0087] The resistor 156 restricts a current supplied from a power supply159. The current supplied from the resistor 156 is supplied to theconnection point of the capacitor 155 and the amplifier circuit 158 as acharging current of the capacitor 155. If the voltage of the connectionpoint of the capacitor 155 and the amplifier circuit 158 exceeds anupper limit, the diode 157 is forward-biased to keep constant thevoltage of the connection point of the capacitor 155 and the amplifiercircuit 158.

[0088]FIG. 9 is a waveform chart of an operation of the SUSPEND/RESUMEsignal control part of the embodiment of the present invention. FIG.9(A) is a waveform of the SUSPEND/RESUME signal supplied to theSUSPEND/RESUME signal control part 152, FIG. 9(B) is a waveform obtainedby differentiating the supplied waveform by the capacitor 155, and FIG.9(C) is an output waveform of the SUSPEND/RESUME signal control part152.

[0089] When the SUSPEND/RESUME button 110 is pressed ON at a time t0,the SUSPEND/RESUME signal is reversed from a HIGH level to a LOW levelas shown in FIG. 9(A).

[0090] When the SUSPEND/RESUME signal is reversed from the HIGH level tothe LOW level as shown in FIG. 9(A), the capacitor 155 discharges, sothat the level of the second end of the capacitor 155 becomes LOW asshown in FIG. 9(B). When the level of the second end of the capacitor155 becomes LOW, the amplifier circuit 157 is switched OFF so that theoutput level of the amplifier circuit 158 becomes LOW as shown in FIG.9(C).

[0091] When the capacitor discharges and the level of the second end ofthe capacitor 155 becomes LOW as shown in FIG. 9(B), the capacitor 155is gradually charged by the current supplied from the resistor 156 tothe second end of the capacitor 155 so that the level of the second endof the capacitor 155 gradually increases.

[0092] Next, when the capacitor 155 is gradually charged so as to reacha predetermined level L0 at a time t1 as shown in FIG. 9(B), theamplifier circuit 158 is switched ON so that the output level thereofbecomes HIGH as shown in FIG. 9(C).

[0093] Next, when the SUSPEND/RESUME button 110 is released at a timingt2, the level of the signal supplied to the first end of the capacitor155 of the SUSPEND/RESUME signal control part 152 becomes HIGH as shownin FIG. 9(A).

[0094] When the level of the first end of the capacitor 155 becomesHIGH, the capacitor 155 is charged so that the level of the second endthereof also attempts to become HIGH. However, the capacitor 155 isbypassed by the diode 157 to be maintained at a certain level determinedby the power supply 159 and the resistor 156. That is, a protruding partindicated by oblique hatching in FIG. 9(B) is restricted so that theoutput of the amplifier circuit 158 is not affected.

[0095] In this case, a LOW-level period T0 shown in FIG. 9(C) is set toa predetermined period by a time constant determined by a capacity ofthe capacitor 155 and a value of the resistor 156. The capacity of thecapacitor 155 and the value of the resistor 156 are provided so that theLOW-level period T0 is set to be shorter than a period during which thechip set 139 does not command the POWER SHUT-OFF operation, that is, aperiod of four seconds.

[0096] Therefore, even if the SUSPEND/RESUME button 110 is kept pressedfor four seconds or longer, the signal supplied to the chip set 139 isreversed from the LOW level to the HIGH level when the predeterminedperiod set by the time constant determined by the capacity of thecapacitor 155 and the value of the resistor 156 passes since theSUSPEND/RESUME button 110 is pressed. Thus, the SUSPEND/RESUME button110 is prevented from shutting off the power of the apparatus.

[0097] Therefore, even if the user unintentionally operates theSUSPEND/RESUME button 110 for four consecutive seconds or longer toperform the SUSPEND or RESUME operation, the POWER SHUT-OFF is preventedfrom being caused.

[0098] A circuit that prevents the SUSPEND/RESUME signal from beingmaintained at the LOW-level for four consecutive seconds or longer isnot limited to the one having the above-described structure. Further,the above-described circuit structure can be realized, without anadditional circuit, by providing the SUSPEND/RESUME button 110 with astructure that prevents the contacts of the SUSPEND/RESUME button 110from being in contact for four seconds or longer in a single operation.

[0099] Thus, according to the electronic apparatus of this embodiment,which apparatus generates a detection signal based on an operation of anoperation means, operates a SUSPEND function based on a state change ofthe generated detection signal, and shuts off the power when a certainstate of the detection signal continues for a predetermined period, aperiod of the certain state of the generated detection signal isrestricted within the predetermined period.

[0100] Further, according to this embodiment, a differentiated waveformof the detection signal generated by a detection signal generation meansis generated so that a binary signal is generated based on the level ofthe generated differentiated waveform.

[0101] Moreover, the electronic apparatus is characterized by includinga limiter that restricts the differentiated waveform of the detectionsignal generated by a differentiating means to a predetermined level.

[0102] According to this embodiment, by restricting the period of thecertain state of the detection signal within the predetermined period,the period of the detection signal is restricted within thepredetermined period even if a SUSPEND/RESUME button is pressed for thepredetermined period or longer. Therefore, even if the SUSPEND/RESUMEbutton is unintentionally pressed for a longer period than necessary,the power is precluded from being shut off, thus preventing the loss ofdata.

[0103] Further, according to the present invention, by restricting thedifferentiated waveform of the detection signal to the predeterminedlevel, an amplifier circuit is provided with a signal whose level isequal to or below the predetermined level, thus preventing a malfunctionof the apparatus.

[0104] As described above, according to this embodiment, by restrictingthe period of a predetermined input operation by an input means withinthe predetermined period, the state of the apparatus is prevented frombeing changed from the first state to the third state even if the inputmeans is operated for the predetermined period or longer. Therefore, anunnecessary state transition can be prevented, thus increasing theoperability of the electronic apparatus.

1. An electronic apparatus changing states thereof based on apredetermined input operation, characterized by comprising: input meansfor performing the predetermined input operation; input operationdetection means for detecting a presence or absence of the predeterminedinput operation to said input means; state transition control means forchanging a state of the apparatus from a first state to a second statewhen said input operation detection means detects an operation of saidinput means, and changing the state of the apparatus to a third statewhen a continuation of the operation of said input means for apredetermined period or longer is detected, the first, second, and thirdstates being different from one another; and nullification means fornullifying the operation of said input means before a passage of thepredetermined period.
 2. The electronic apparatus as claimed in claim 1, characterized in that: said input operation detection means comprisesdetection signal generation means for generating a detection signal of acertain state based on the operation of said input means; and saidnullification means comprises detection signal restriction means forrestricting a period of the certain state of the detection signal withinthe predetermined period.
 3. A control circuit of an electronicapparatus which comprises input means for commanding a transition ofstates of the apparatus, input operation detection means for detecting apresence or absence of a predetermined input operation by said inputmeans, state transition control means for changing a state of theapparatus from a first state to a second state when said input operationdetection means detects an operation of said input means, and changingthe state of the apparatus to a third state when a continuation of theoperation of said input means for a predetermined period or longer isdetected, the first, second, and third states being different from oneanother, said control circuit being characterized by comprising:nullification means for nullifying the operation of said input meansbefore a passage of the predetermined period.
 4. The control circuit asclaimed in claim 3 , characterized in that: said input operationdetection means comprises detection signal generation means forgenerating a detection signal of a certain state based on the operationof said input means; and said nullification means comprises detectionsignal restriction means for restricting a period of the certain stateof the detection signal within the predetermined period.
 5. A method ofcontrolling an electronic apparatus changing states thereof based on apredetermined input operation, characterized by comprising: a first stepof detecting a presence or absence of the predetermined input operation;a second step of changing a state of the apparatus from a first state toa second state when the predetermined input operation is detected insaid first step, the first and second states being different from eachother; a third step of changing the state of the apparatus to a thirdstate when a continuation of the operation of the predetermined inputoperation for a predetermined period or longer is detected, the thirdstate being different from the first and second states; and a fourthstep of nullifying the predetermined input operation before a passage ofthe predetermined period.